MILPRF50884F
APPENDIX A
A.3.5.3 Coverlayer (including coverfilm and cover coat). Unless otherwise specified, the requirements specified in
A.3.5.3.1 through A.3.5.3.6 shall apply to coverlayers, coverfilms, and cover coats. When the term coverlayer is used
herein, it also applies to both coverfilms and cover coats.
A.3.5.3.1 Coverage. Coverlayer coverage imperfections (such as blisters, pits, skips, and voids) shall be
acceptable providing the imperfection complies with the following:
a.
The coverlayer imperfection shall not bridge by blisters or expose isolated conductors whose spacing is less
than the electrical spacing required for the voltage range and environmental condition specified in the
applicable design standard.
b.
In areas containing parallel conductors, the coverlayer imperfection shall not expose isolated conductors
whose spacing is less than .020 inch (0.5 mm) unless one of the conductors is a test point or other feature
area which is purposely left uncoated for subsequent operations.
c.
The exposed conductor shall not be bare copper.
d.
The coverlayer imperfection does not expose plated holes or via holes that are to be tented or filled by
coverlayer.
e.
Blisters in the coverlayer shall not exceed the following: Two for each side, maximum size .010 inch
(0.25 mm) in longest dimension, does not reduce electrical spacing between conductors by more than 25
percent.
f.
Pits and voids in non-conductor areas shall be acceptable provided they have adherent edges and do not
exhibit lifting or blisters in excess of that allowed in A.3.5.3.1.e.
g.
The coverlayer may tent or plug via holes as specified (see A.3.1.1). Coverage between closely spaced
surface mount lands shall be as specified.
h.
The coverlayer does not need to be flush with the surface of the land.
A.3.5.3.2 Delamination (see figure F8). The coverlayer shall be uniform and free of delaminations, such as
creases, soda strawing, and wrinkles. Coverlayer delamination or nonlamination shall be acceptable, providing
such imperfections do not violate A.3.5.1.3.1 and the following conditions are met:
a.
At random locations away from conductors if each delamination is no larger than .01 square inch (6.45
square mm) and is not within .040 inch (1.0 mm) of the printed wiring board edge or coverlayer access hole
or opening. The total number of the above delaminations shall not exceed three in any 1 square inch (645
square mm) of coverlayer surface area.
b.
Along conductor edges, the total delamination does not exceed either .02 inch (0.51 mm) in width or 20
percent of the spacing between adjacent conductors, whichever is smaller.
c.
When design requires coverage to the edge of flexible sections; chipping, delamination, lifting, or separation
of the coverlayer along the edge of flexible sections shall not penetrate more than .05 inch (1.3 mm) or 50
percent of the distance to the closest conductor, whichever is less.
d.
There shall be no coverlayer delamination along the outer edges of the coverlayer or openings of the
coverlayer that reduces the seal below minimum edge to conductor spacing (see A.3.5.1.1).
e.
There shall be not more than 3 coverlayer delaminations that exceeds 1.0 square inch (25.4 square mm) in
surface area.
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