MILPRF50884F
APPENDIX A
A.3.5.3.5 Thickness. The coverlayer thickness shall be as specified (see A.3.1.1).
A.3.5.3.6 Wicking of metallic conductor surface finish materials (plated metals or solder) (see figure F10). The
wicking of plating metals or solder shall not extend into a bend or flex transition area and shall meet the conductor
spacing requirements. When wicking under coverlayers is present in non-bend or flex transition areas, the
penetration of metallic conductor surface finish materials (plated metals or solder) not exceed .012 inch (0.3 mm).
A.3.5.4 Dimensions of features (interface and physical dimensions). The finished printed wiring boards shall meet
the interface and physical dimensions specified (see A.3.1.1). The dimensional requirements includes items such as
cutouts, overall thickness, periphery, and other design features as specified. In the event that a dimensional
characteristics is not specified, the applicable class 3 of IPC2221 design default for that characteristic shall apply.
A.3.5.4.1 Conductor pattern feature accuracy. Conductor pattern feature accuracy shall be as specified.
A.3.5.4.2 Hole pattern accuracy. The accuracy of the hole pattern (size and location) on the printed wiring board
shall be as specified (see A.3.1.1).
A.3.5.4.3 Hole size. The hole size and tolerance shall be as specified. Unless otherwise specified, hole size
tolerance shall be applied after plating. Nodules or rough plating in platedthrough holes shall not reduce the hole
diameter below the minimum limits specified.
A.3.5.4.4 Edge board contacts edge condition. The end or beveled edge of edge board contacts shall be smooth
with no burrs, roughness, or lifted plating. There shall be no separation of the edge board contacts from the base
material or any loose reinforcement fibers on the beveled edge. Exposed copper on the end or beveled edge of the
edge board contact shall be acceptable. Conductor finish plating or coating shall comply with the requirements of
A.3.5.5 Solder mask (when applicable). The cured solder mask shall not exhibit any chalking, crazing, peeling,
skipping, softening, swelling, wicking, or wrinkles in excess of the limits specified herein. Unless otherwise specified
A.3.5.5.1 BGA lands. BGA lands using solder maskdefined lands or solder dam designs shall comply with the
class 3 acceptable conditions of IPCA600.
A.3.5.5.2 Coverage. Solder mask coverage imperfections (such as blisters, skips, and voids) shall be acceptable
providing the imperfection meets all of the following:
a.
The solder mask imperfection shall not expose two adjacent conductors whose spacing is less than the
electrical spacing required for the voltage range and environmental condition specified in the applicable
design standard.
b.
In areas containing parallel conductors, the solder mask imperfection shall not expose two isolated
conductors whose spacing is less than .020 inch (0.5 mm) unless one of the conductors is a test point or
other feature area which is purposely left uncoated for subsequent operations.
c.
The exposed conductor shall not be bare copper.
d.
The solder mask imperfection does not expose via holes that are required to be tented.
e.
Bubbles, pits or voids in non-conductor areas shall be acceptable if they have adherent edges and do not
exhibit blistering or lifting in excess of that allowed in A.3.7.4.4.
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