MILPRF50884F
APPENDIX A
A.3.6.4.3 Copper plating defects (see figures G13 and G14). Unless otherwise specified (see A.3.1.1), a 20
percent reduction of the specified copper plating thickness shall be acceptable if it is non-continuous (isolated; not
more than 10 percent of the composite board thickness). Any copper plating less than 80 percent of the specified
thickness shall be treated as a copper plating void.
A.3.6.4.4 Copper plating voids (see figure G15). The copper plating in the plated-through holes shall not exhibit
any void in excess of the following:
a.
There shall be no more than one plating void for each panel, regardless of length or size.
b.
There shall be no plating void in excess of 5 percent of the total printed wiring board thickness.
c.
There shall be no plating voids evident at the interface of an internal conductive layer and plated hole wall.
Conductor finish plating or coating material between the base material and copper plating (i.e., behind the hole wall
copper plating) is evidence of a void. Any plated-through hole exhibiting this condition shall be counted as having
one void for panel acceptance purposes.
A.3.6.4.5 Wicking of copper plating (see figure G16). When measured from the edge of the drilled hole, wicking
of copper plating into the base material shall be acceptable provided it does not reduce the conductor spacing below
the minimum clearance spacing requirements specified (see A.3.1.1) and the wicking complies with the following:
a.
If etchback is specified, wicking does not extend more than .005 inch (0.13 mm) maximum.
b.
When etchback is not specified, wicking does not extend more than .004 inch (0.10 mm) maximum.
A.3.6.5 Conductive interfaces and separations. The term conductive interfaces shall be used to describe the
junction between the hole wall plating or coating and the surfaces of internal and external layers of copper or metal
foil. The interface between platings and coating (electroless copper, direct metallization copper, nonmetallic
conductive coatings, or vacuum deposited copper, and electrolytic copper, whether panel or pattern plated) shall also
be considered a conductive interface.
A.3.6.5.1 Copper to copper interfaces (see figure G17). Except along the vertical edge of the external copper foil,
there shall be no separations or contamination between the hole wall copper conductive interfaces. Conductive
interface separations along the vertical edge of the external copper foil shall be acceptable.
A.3.6.5.2 Dissimilar metal interfaces. For printed wiring board designs containing metal cores with dissimilar
metals (such as copper-invar-copper), contamination or separation at the conductive interface shall not exceed 20
percent of the thickness of the dissimilar metal.
A.3.6.6.1 Thickness. For designs that specify copper plating for via protection, the minimum via cap plating
thickness over filled vias shall be as specified (see A.3.1.1). If not specified, the minimum via cap copper plating
thickness over filled vias shall be in accordance with the minimum wrap copper plating thickness specified in
A.3.6.6.2 Cap plating imperfections. When cap plating of a filled via is specified, voids in the plating over the via fill
shall not be acceptable. Separation of the via cap plating to via fill material shall be acceptable. Separation of the via
cap plating to underlying plating shall not be acceptable. Depressions (dimples) below the surface of the land shall
be no greater than .003 inch (0.08 mm). Protrusions (bumps) of the cap plating above the surface of the land shall be
no greater than .002 inch (0.051 mm).
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