MIL-DTL-62738A(AT)
3.3.2 Complementary metal oxide semiconductor (CMOS) logic levels. Unless otherwise
specified (see 6.2), CMOS logic levels accepted by and output from the PWA shall be as follows:
Input High (Logic Level 1) = 3.5 Vdc minimum (min)
Input Low (Logic Level 0) = 1.5 Vdc maximum (max.)
Output High (Logic Level 1) = 4.5 Vdc min
Output Low (Logic Level 0) = 0.5 Vdc max.
Output High at E4 (Logic Level 1) = 7.0 Vdc min
Output Low at E4 (Logic Level 0) = 0.5 Vdc max.
3.3.3 PWA set up. The PWA shall be set up with the following characteristics for the
following requirements: E5 and E9 shall be at ground; E7 shall be at 5 +0.1 Vdc; E6 shall be at
24 Vdc; input signals shall be applied at E1 with respect to E2 or at E10 with respect to E11. An
18 +1.8 kilohms (kohm) pull-up resistor shall be connected from E4 to 8.0 +0.4 Vdc.
3.3.4 Input peak limiting. A signal with source impedance of 100 +10 ohms and peaks of
1000 +100 V shall be limited to less than 400 V peaks when applied at E1 with respect to E2.
3.3.5 Points voltage output signal. When 50 +17% duty cycle square wave with a source
impedance of 10 +1 ohms and amplitude from zero to the same voltage as that at E6 is applied at
E1 with respect to E2, the signal at E3 with respect to E2 shall be a positive square wave with
amplitude of 6.8 +0.6 V.
3.3.6 Ignition signal output. When a square wave of amplitude from zero to the same
voltage as the voltage at E6 is applied at E1 with the respect to E2, the signal at E4 with respect
to E5 shall have the same frequency as the input signal. The rising edge of the signal at E4 shall
be between 130 and 800 microseconds (µs) after the falling edge of the signal at E1. The output
shall conform to the logic levels given in 3.3.2.
3.3.7 Ignition inhibit. When a square wave of the amplitude from zero to the same
voltage as that at E6 is applied at E1 with respect to E2 from a source with output impedance of
10 +1 ohms and the capability of sourcing not less than 2 amperes, a logic level 0 applied at E8
shall cause the amplitude of the signal applied at E1 to be pulled down to 6 +1 V.
3.3.8 Soldering. Soldering shall meet or exceed the requirements of
ANSI/IPC J-STD-001 (see 4.2).
3.4 Interface requirements.
3.4.1 Overall envelope. Overall envelope of the PWA shall be in accordance with
Drawing 12258887.
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