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MIL-DTL-62740 Printed Wiring Assembly, Special CircuitsThis specification covers a Special Circuits Printed Wiring Assembly referred to herein as the PWA. This is one of six printed wiring assemblies which comprise the Simplified Test Equipment/Internal Combustion Engine-Reprogrammable \(STE/ICE-R\) Vehicle Test Meter \(VTM\) \(see Drawing 12259265\).

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MIL-DTL-62740A(AT)
4.2.3.8 Divide by n + 1 counter. A 0 to 5 Vdc, 700 kilohertz (kHz) square wave shall be
applied at P1-51. A HEXAD pattern 02 shall be applied at P1-21 through P1-28 and the
waveform of figure 2 shall be applied. For each HEXAD input specified in table V, the HEXAD
pattern shall be applied at P1-21 through P1-28 and the waveform of figure 1 shall be applied.
The frequency of the signal at U9 pins 14 and 15 shall be measured. This measured frequency
shall be verified to conform to the corresponding limits specified in table V for the appropriate
HEXAD input to determine conformance to 3.3.8.
TABLE V. Divide by n + 1 counter. (n ≠ 0).
Hex
Frequency
Input
Output
04
140.0 kHz
70.0 kHz
09
0E
46.7 kHz
35.0 kHz
13
18
28.0 kHz
1D
23.3 kHz
22
20.0 kHz
27
17.5 kHz
15.6 kHz
2C
31
14.0 kHz
36
12.7 kHz
11.7 kHz
3B
40
10.8 kHz
4.2.3.9 Interrupt and flag select. To determine conformance to 3.3.9, a 0 to 5 Vdc,
700 kHz square wave shall be applied to P1-51. A HEXAD pattern 03 shall be applied at P1-21
through P1-28 and the waveform of figure 2 shall be applied. A HEXAD pattern 01 shall be
applied at P1-21 through P1-28 and the waveform of figure 1 shall be applied. The frequency of
the signal at U3-7 shall be verified to be 700 kHz. A HEXAD pattern 0A shall be applied at
P1-21 through P1-28 and the waveform of figure 2 shall be applied. The frequency of the signal
at U21 pin 14 shall be verified to be 350 kHz.
4.2.3.10 Test push button debouncer. To determine conformance to 3.3.10, a logic level
0 shall be applied at P1-50 and U6 pin 3 shall be verified to be at logic level 0. Simultaneously a
logic level 0 shall be applied to P1-52, and P1-50 shall be allowed to float. U6 pin 3 shall be
verified to change to a logic level 1 in less than 400 ns. Simultaneously a logic level 0 shall be
applied to P1-50, and P1-52 shall be allowed to float. U6 pin 3 shall be verified to change to a
logic level 0 in less than 400 ns.
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