MIL-DTL-62740A(AT)
rising edge of the signal at U3 pin 5 shall occur between 343 and 454 µs after the rising edge of
the signal at P1-66.
3.3.15 Full wave rectifier.
3.3.15.1 Full wave rectifier on. With a logic level 1 at U13 pins 10 and 11 and a signal
with amplitude of 2 V alternating current (ac) peak-to-peak at a frequency of 100 Hz applied at
P1-78, the signal measured at P1-76 shall be positive. The signal at U13-4 shall have a positive
pulse of twice the input. The signal at U13-4 shall have no more than 30 millivolts direct current
(mVdc) difference between adjacent peaks and no more than 50 mVdc difference between
adjacent low points.
3.3.15.2 Full wave rectifier off. With a logic level 0 at U13 pins 10 and 11 and a signal
with amplitude between 100 mVdc and 5 Vdc and frequency between 10 and 500 Hz applied at
P1-78, the signal at P1-76 shall have the same frequency as the signal applied at P1-78. With a
signal source impedance at P1-78 of less than 100 ohms and an output impedance at P1-76 of
greater than 50 kohms, the amplitude of the signal at P1-76 shall not be less than 95 percent (%)
of the amplitude of the signal at P1-78.
3.3.16 Multiplexor. Logic levels present at U3 pins 6, 5, 4, or 3 shall be present at U3
pin 7 according to the logic levels at U3 pins 14 and 2 and table III. Logic levels shall be present
at U3 pin 7 no greater than 490 ns after they are applied at U3 pins 6, 5, 4, and 3.
TABLE III. Multiplexor.
Input:
U3 Pin
Output to U3 pin 7
14
2
from pin:
6
0
0
5
1
0
4
0
1
3
1
1
3.3.17 ATE Test. The PWA shall pass TACOM approved ATE test installed in TACOM
approved ATE or equivalent.
3.3.18 Soldering. Soldering shall meet or exceed the requirements of
ANSI/IPC J-STD-001.
3.4 Interface requirements. Each PWA shall accommodate the following requirements.
3.4.1 Overall envelope. Overall envelope of the PWA shall be in accordance with
drawing 12258774.
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