MIL-DTL-62740A(AT)
3.3.2 Output voltages.
3.3.2.1 12 Volts (V) reference. The voltage at P1-9 and P1-10 shall be 12.0 + 0.5 Vdc.
U25 shall be capable of sourcing 100 milliamperes (mA) while maintaining the specified output
voltage.
3.3.2.2 8 V reference. The voltage at P1-7 and P1-8 shall be 8.0 + 0.4 Vdc. U24 shall be
capable of sourcing 100 mA while maintaining the specified output voltage.
3.3.2.3 -8 V reference. The voltage at P1-17 and P1-18 shall be -8.0 + 0.4 Vdc. U26
shall be capable of sourcing 200 mA while maintaining the specified output voltage.
3.3.3 Complementary metal oxide semiconductor (CMOS) logic levels. Unless otherwise
specified (see 6.2), CMOS logic levels accepted by and output from the PWA shall be as follows:
Input High (Logic Level 1) = 3.5 Vdc minimum (min.)
Input Low (Logic Level 0) = 1.5 Vdc maximum (max.)
Output High (Logic Level 1) = 4.5 Vdc min.
Output Low (Logic Level 0) = 0.5 Vdc max.
3.3.4 Latches. (NOTE: A "/" following a capitalized logic name denotes logic negation.)
3.3.4.1 Output clocks. The signal at U27-4 shall be determined by the signals at P1-31
(IOB/3) and P1-37 (OEN-Q/) and shall conform to the waveforms shown in figure 1. The signal
at U27-11 shall be determined by the signals at P1-32 (IOC/4) and P1-37 (OEN-Q/) and shall
conform to the waveforms shown in figure 2. The signal at U27-10 shall be determined by the
signals at P1-33 (IOD/5) and P1-37 (OEN-Q/) and shall conform to the waveforms shown in
figure 3. The signal at U27-3 shall be determined by the signals at P1-34 (IOE/6) and P1-37
(OEN-Q/) and shall conform to the waveforms shown in figure 4.
3.3.4.2 Output latches. Logic levels at P1-21 through P1-26 (BUS 0 through BUS 5)
shall be latched by U16 and appear at U16 pins 7, 5, 2, 10, 12, and 15, respectively, when clocked
by U27-4 as shown in figure 1. Logic levels at P1-21 through P1-26 shall be latched by U17 and
appear at U17 pins 7, 5, 2, 10,12, and 15, respectively, when clocked by U27-11 as shown in
figure 2. Logic levels at P1-21 through P1-26 shall be latched by U18 and appear at U18 pins 7,
5, 2, 10, 12 and 15, respectively, when clocked by U27-10 as shown in figure 3, except a logic
level 1 at U18-2 shall be 2.4 Vdc. Logic levels at P1-21 through P1-28 (BUS 0 through BUS 7)
shall be latched by U19 and U20 and appear at U19 pins 7, 13, 14, and 4, and U20 pins 14, 4, 7,
and 13, respectively, when clocked by U27-3 as shown in figure 4.
4
For Parts Inquires submit RFQ to Parts Hangar, Inc.
© Copyright 2015 Integrated Publishing, Inc.
A Service Disabled Veteran Owned Small Business