MILPRF55110G
APPENDIX A
A.3.5.1
A.3.5.1 Base materials.
A.3.5.1.1
A.3.5.1.1 Edges of base material. Burrs, crazing, nicks, and haloing along the edges of printed wiring boards,
including edges of cutouts and edges of non-plated-though holes, shall be acceptable provided the penetration does
not reduce the edge spacing by more than 50 percent of the edge spacing specified (see A.3.1.1) or .10 inch (2.5
mm), whichever is smaller. If no requirement for edge spacing is specified (see A.3.1.1), the penetration shall not
exceed .10 inch (2.5 mm). Panels that are partially routed with breakaway tabs or scored for printed board removal
shall meet the de-panelization requirements specified (see A.3.1.1).
A.3.5.1.2
A.3.5.1.2 Surface imperfections. Surface imperfections (such as scratches, pits, dents, cuts or exposed
reinforcement fibers, and weave texture) shall be acceptable providing the imperfection meets the following:
a.
The base material reinforcement material (woven or non-woven fiber) is not cut, disturbed, or exposed.
b.
The imperfection does not bridge between conductors (weave texture may bridge conductors).
c.
The dielectric spacing between the imperfection and conductors does not reduce conductor spacing below
the specified minimum requirements (see A.3.1.1).
A.3.5.1.3
A.3.5.1.3 Subsurface imperfections (see A.6.8). Subsurface imperfections (such as blistering, haloing, and
delamination) shall be acceptable providing the imperfection meets the following:
a.
The imperfection is translucent.
b.
The imperfection does not bridge more than 25 percent of the distance between conductors or plated-
through holes. No more than two percent of the printed wiring board area on each side shall be affected.
A.3.5.1.3.c
c. The imperfection does not reduce conductor spacing between adjacent conductors below the minimum
requirements specified (see A.3.1.1).
d.
The imperfection does not propagate as a result of testing (such as rework simulation, thermal stress, or
thermal shock).
e.
Color variations or mottled appearance in bond enhancement treatments shall be acceptable. Random
areas of missing bond enhancement treatment shall not exceed 10 percent of the total conductor surface
area of the affected layer.
A.3.5.1.3.1
A.3.5.1.3.1 Foreign inclusions. Foreign inclusions shall be permitted when they meet the following:
a.
The foreign inclusions are translucent.
b.
The foreign inclusion is located at least .010 inch (0.25 mm) from the nearest conductor.
c.
The foreign inclusion does not reduce the spacing between conductors below the minimum conductor
spacing specified (see A.3.1.1). If not specified, the inclusion does not reduce the conductor spacing by
more than 50 percent.
d.
The foreign inclusions longest dimension is no greater than .032 inch (0.81 mm) in circuitry areas. Inclusions
in non-circuitry areas have no maximum dimension requirement.
e.
When the base material specification allows for more or larger inclusions, those inclusions are allowed in the
finished printed board, up to the size and quantity defined by the base material specification provided that
the inclusion does not violate the conductor spacing requirements of A.3.5.1.3.c.
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