MILPRF55110G
APPENDIX A
A.3.5.1.3.2
A.3.5.1.3.2 Subsurface spots. Subsurface spots shall be permitted when they meet any of the following:
a.
The spots are translucent.
b.
The spots are known to be weave texture and not delamination or disbonding.
c.
The spots are isolated white spots that are at least .010 inch (0.25 mm) from the nearest conductor or that
do not propagate as a result of any soldering operation (gelation particles are acceptable regardless of
location).
A.3.5.1.3.3
A.3.5.1.3.3 Measling and crazing. Measling and crazing shall not exceed the requirements specified in IPC-A-600,
class 3, for bare printed wiring boards.
A.3.5.2
A.3.5.2 Conductor pattern.
A.3.5.2.1
A.3.5.2.1 Annular ring, external (see figure A1). The minimum external annular ring shall be as specified (see
A.3.1.1). If not specified, the minimum external annular ring shall be .002 inch (0.051 mm) for plated through holes
and .006 inch (0.152 mm) for unsupported holes. Unless otherwise specified, the external annular ring may have, in
isolated areas, a 20 percent reduction of the minimum external annular ring specified (see A.3.1.1), due to defects
such as pits, dents, nicks, and pinholes.
A.3.5.2.2
A.3.5.2.2 Conductor spacing. The conductor spacing, including tolerance, shall be as specified (see A.3.1.1). The
minimum edge spacing shall be as specified (see A.3.1.1). If no conductor spacing tolerance is specified, a reduction
in the conductor spacing of 10 percent above the specified spacing, due to isolated defects or misregistration, shall be
considered acceptable.
A.3.5.2.3
A.3.5.2.3 Conductor width. The conductor width(s) shall be as specified (see A.3.1.1).
A.3.5.2.4
A.3.5.2.4 Conductor pattern imperfections (see figure A2). The conductor pattern shall contain no cracks, splits
or tears. Unless otherwise specified (see A.3.1.1), any combination of edge roughness, nicks, pinholes, cuts or
scratches exposing the base material shall not reduce each conductor width more than 20 percent of its minimum
specified width. There shall be no occurrence of the 20 percent reductions greater than .50 inch (12.70 mm) or 10
percent of a conductor length, whichever is less.
A.3.5.2.5
A.3.5.2.5 Conductor width reduction (see figure A2). Allowable reduction in the conductor width, due to isolated
defects or misregistration, shall not exceed 20 percent of the minimum conductor width.
A.3.5.2.6
A.3.5.2.6 Conductor finish coverage. The conductor finish plating or coating shall completely cover the basis metal
of the conductive pattern. Complete conductor coverage by solder does not apply to the vertical conductor edges.
There shall be no evidence of any lifting or separation of conductor finish plating or coating from the surface of the
conductive pattern. There shall be no whiskers of solder or plating on the surface of the conductive pattern. For
designs using solder resist over bare conductors, it shall be acceptable to have up to .010 inch (0.25 mm) of exposed
base metal at the interface between the solder resist and the basis metal conductor finish. For design requiring
unfused tin-lead plating as a final conductor finish coverage, the thickness shall be as specified (see A.3.1.1 and
A.3.3).
A.3.5.2.7
A.3.5.2.7 Solderable surface mount lands and wire bond pads. The allowable imperfections along the external
edges of lands, or to the surface of the land of surface mount lands or wire bond pads, shall not exceed the
requirements specified in IPC-A-600, class 3, for surface plating - wire bond pads.
A.3.5.3
A.3.5.3 Dimensions of features. The finished printed wiring board shall meet the dimensional requirements for
features such as cutouts, periphery, overall board thickness, etc. as specified (see A.3.1.1).
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