MIL-DTL-62741A(AT)
3.3.2 Complementary metal oxide semiconductor (CMOS) logic levels. Unless otherwise
specified (see 6.2), CMOS logic levels accepted by and output from the PWA shall be as follows:
Input High (Logic Level 1) = 3.5 Vdc minimum (min)
Input Low (Logic Level 0) = 1.5 Vdc maximum (max.)
Output High (Logic Level 1) = 4.5 Vdc min
Output Low (Logic Level 0) = 0.5 Vdc max.
3.3.3 Input/output logic. (NOTE: A "/" following a capitalized logic name denotes logic
negation.)
3.3.3.1 Output clocks. The signal at U7-10 shall be determined by the signals at P1-29
(IO9/1) and P1-37 (OEN-Q/) and shall conform to the waveforms shown in figure 1. The signal
at U7-4 shall be determined by the signals at P1-30 (IOA/2) and P1-37 (OEN-Q/) and shall
conform to the waveforms shown in figure 2.
3.3.3.2 Output latches. Logic levels at P1-21 through P1-26 (BUS 0 through BUS 5)
shall be latched by U1 and appear at U1 pins 2, 5, 7, 10, 15 and 12, respectively, when clocked by
U7-10 as shown in figure 3. Logic levels at P1-21 through P1-26 (BUS 0 through BUS 5) shall
be latched by U2 and appear at U2 pins 15, 12, 10, 7, 2, and 5, respectively, when clocked by
U7-4 as shown in figure 4.
3.3.3.3 Voltage level shifters. Logic levels present at U3, U4, and U5 pins 3, 6, 10, and
14 shall be shifted as shown below and shall be present at U3, U4, and U5 pins 4, 5, 13, and 11,
respectively, within 600 nanoseconds (ns) of their application to the input.
Output High (Logic Level 1) = [(voltages at U5 pin 16) - 0.30 Vdc] minimum
Output Low (Logic Level 0) = 0.5 Vdc maximum
3.3.3.4 Input clocks. The signal at U7-3 shall be determined by the signals present at
P1-29 (I09/1) and P1-36 (MRD/) and shall conform to the waveforms shown in figure 5. The
signal at U7-11 shall be determined by the signals present at P1-30 (I0A/2) and P1-36 (MRD/)
and shall conform to the waveforms shown in figure 6.
3.3.3.5 Input buffers. Logic levels present at U16 pins 12, 14, and U24 pins 2, 4, 14, 12,
10, and 6 shall be present on P1-28 through P1-21 (BUS 7 through BUS 0) when the signal at
U7-3 is active as shown in figure 7. Logic levels present at U6 pins 6, 2, 4, 10, and U16 pins 6, 4,
2, and 10 shall be present on P1-28 through P1-21 when the signal at U7-11 is active as shown in
figure 8. The signal present at P1-40 shall be present at U6-11 within 90 ns of its application at
P1-40 regardless of any other signal.
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