MIL-DTL-62741A(AT)
3.3.4 Internal logic levels. Logic levels accepted by U8, U9, U13, U14, U18, U19, U20,
U21, U22, U23, and U26 shall be:
Input High (Logic Level 1) = 5.6 Vdc min
Input Low (Logic Level 0) = 2.4 Vdc max.
3.3.5 Input channel Mux select. The inputs specified in table II shall be routed to U10
pins 1 (+) and 3 (-) when the corresponding bit pattern from table II is applied to BUS 0 through
BUS 5 in accordance with the waveforms shown in figure 3.
3.3.6 Input channel attenuation. The ratio of the magnitude of the input voltage to the
magnitude of the voltage across U10 pins 1 and 3 shall be as stated by the attenuation ratio in
table II for the channel selected in accordance with the requirements of paragraph 3.3.5. The
attenuation accuracy shall be as stated in table II for the selected channel (if applicable).
TABLE II. Input channel attenuation and select.
(+)
(-)
Attenuation
BUS
Input voltage
Input
Input
Ratio Accuracy
5
4
3
2
1
0
range
P1-98
P1-99
1:1
-
0
0
0
0
0
0
+5V
P1-96
P1-93
1:1
-
0
0
0
0
0
1
+5V
P1-94
P1-97
1:1
-
0
0
0
0
1
0
+5V
P1-100
P1-95
1:1
-
0
0
0
0
1
1
+5V
P1-90
P1-91
1:1
-
0
0
0
1
0
0
+5V
P1-88
P1-85
1:1
-
0
0
0
1
0
1
+5V
P1-86
P1-89
1:1
-
0
0
0
1
1
0
+5V
P1-92
P1-87
1:1
-
0
0
0
1
1
1
+5V
P1-82
P1-83
1:1
1/
0
0
1
0
0
0
+5V
P1-80
P1-77
1:1
-
0
0
1
0
0
1
+5V
P1-78
P1-81
1:1
-
0
0
1
0
1
0
+5V
P1-84
P1-79
1:1
-
0
0
1
0
1
1
+5V
P1-61
P1-59
1:1
-
0
0
1
1
0
0
+5V
P1-55
P1-53
10:1
0.2%
0
0
1
1
1
0
+ 50 V
P1-51
P1-49
7:1
0.1%
0
0
1
1
1
1
+ 35 V
+ 35 V
P1-47
P1-49
7:1
0.1%
0
1
X
X
0
0
+ 35 V
P1-45
P1-50
7:1
0.1%
0
1
X
X
0
1
+ 35 V
P1-54
P1-49
7:1
0.1%
0
1
X
X
1
0
+ 35 V
P1-52
P1-49
7:1
0.1%
0
1
X
X
1
1
+ 15 V
P1-9
P1-1
3:1
0.1%
1
0
X
0
0
0
P1-48
P1-1
7:1
0.1%
1
0
X
0
0
1
+ 35 V
P1-44
P1-1
7:1
0.1%
1
0
X
0
1
0
+ 35 V
+ 35 V
P1-46
P1-1
7:1
0.1%
1
0
X
0
1
1
+ 35 V
P1-42
P1-1
7:1
0.1%
1
0
X
1
0
0
+5V
P1-58
P1-1
1:1
-
1
0
X
1
0
1
+5V
P1-62
P1-1
1:1
2/
1
0
X
1
1
0
5
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