MIL-PRF-31032/1B
3.5 External visual and dimensional requirements. Printed board test specimens (the finished printed boards or
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supporting test coupons, as applicable) shall conform to the requirements specified in 3.5.1 through 3.5.5.5.
3.5.1 Base material.
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3.5.1.1 Edges of base material. Burrs, chips, delaminations, haloing, nicks, and other penetrations along the base
material edges of completed printed boards shall be acceptable provided the defect does not reduce the edge
spacing specified by more than 50 percent.
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3.5.1.2 Surface imperfections. Surface imperfections (such as cuts, dents, pits, scratches, or exposed
reinforcement material fibers) shall be acceptable providing the following conditions are met:
a.
The imperfections do not bridge between conductors.
b.
The dielectric spacing between the imperfection and a conductor is not reduced below the specified
minimum conductor spacing requirements.
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3.5.1.3 Subsurface imperfections. Subsurface imperfections (such as blistering, delamination, foreign inclusions,
haloing, etc.) shall be acceptable providing the following conditions are met:
a.
The imperfections do not bridge more than 25 percent of the distance between conductors or plated-through
holes. No more than two percent of the printed board area on each side shall be affected.
b.
The imperfections do not reduce conductor or dielectric spacing below the specified minimum requirements.
c.
The imperfections do not propagate as a result of testing (such as rework simulation, thermal stress, or
thermal shock).
d.
The longest dimension of any single imperfection is no greater than 0.80 mm (.032 inch). In non-circuitry
areas, the maximum size shall not be greater than 2.00 mm (.079 inch) in the longest dimension or 0.01
percent of the printed board area, maximum.
NOTE: Color variations or mottled appearance in bond enhancement treatments shall be acceptable.
3.5.2 Conductor pattern.
3.5.2.1 Annular ring, external. The external annular ring shall be as specified. Unless otherwise specified, the
external annular ring may have, in isolated areas, a 20 percent reduction of the specified external annular ring due to
defects such as pits, dents, nicks, or pinholes.
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3.5.2.2 Bonding of conductor to base material and lifted lands. There shall be no peeling or lifting of any land or
conductor patterns from the base material. The completed printed board shall not exhibit any lifted land. (NOTE:
See 3.6.11 for allowances for the acceptable lifting of terminal pads, i.e. lifted lands, following the thermal stress test,
rework simulation, and thermal shock testing.)
3.5.2.3 Conductor imperfections. The conductor pattern shall contain no cracks, splits, or tears. Unless otherwise
specified, any combination of edge roughness, nicks, pinholes, cuts, or scratches exposing the base material shall not
reduce each conductor width by more than 20 percent of its minimum specified width. There shall be no occurrence
of the 20 percent reductions greater than 13.0 mm (.51 inch) or 10 percent of a conductor length, whichever is less.
3.5.2.4 Conductor finish. The conductor finish shall be as specified.
3.5.2.4.1 Coverage. The conductor finish shall completely cover the exposed conductor pattern. Complete
coverage does not apply to the vertical conductor edges.
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