MILPRF55110G
APPENDIX A
A.3.5.4
A.3.5.4 Hole pattern accuracy. The accuracy of the hole pattern, sizes and locations, on the printed wiring board
shall be as specified (see A.3.1.1).
A.3.5.5
A.3.5.5 Lifted lands. There shall be no lifted lands on the deliverable, non-thermal stressed printed wiring board.
A.3.5.6
A.3.5.6 Registration, external (method I). Registration of external lands shall be satisfied if the external layers
meet the specified annular ring requirements (see A.3.1.1 and A.3.5.2.1). Misregistration shall not reduce the
minimum external annular ring below its specified limits.
A.3.5.7
A.3.5.7 Solder resist (when applicable). Unless otherwise specified, the solder resist requirements specified in
A.3.5.7.1 through A.3.5.7.5 shall apply.
A.3.5.7.1
A.3.5.7.1 Coverage. Solder resist coverage imperfections (such as blisters, delaminations, pits, skips, wrinkles,
and voids) shall be acceptable providing the imperfection meets all of the following:
a.
The solder resist imperfection shall not expose two adjacent conductors whose spacing is less than the
electrical spacing required for the voltage range and environmental condition specified in the applicable
design standard.
b.
In areas containing parallel conductors, the solder resist imperfection shall not expose two isolated
conductors whose spacing is less than 0.5 mm (.020 inch) unless one of the conductors is a test point or
other feature area which is purposely left uncoated for subsequent operations.
c.
The exposed conductor shall not be bare copper.
d.
The solder resist imperfection does not expose via holes that are to be tented or filled by solder resist.
e.
Pits or voids in non-conductor areas shall be acceptable if they do not exhibit blistering or lifting in excess of
that allowed in A.3.7.4.6.
A.3.5.7.2
A.3.5.7.2 Discoloration. Discoloration of metallic surfaces under the cured solder resist shall be acceptable.
A.3.5.7.3
A.3.5.7.3 Registration (see figure A3). The solder resist shall be registered to the land or terminal patterns in
such a manner as to meet the requirements specified (see A.3.1.1). If no requirements are specified, the following
apply:
a.
For plated-through holes and vias, the following shall apply:
(1) Solder resist misregistration onto plated-through component hole lands (plated-through holes to which
solder connections are to be made) shall not reduce the external annular ring below the specified
minimum requirements.
(2) Solder resist shall not encroach into plated-through hole barrels or onto other surface features (such as
connector fingers, or lands of unplated holes) to which solder connections will be made.
(3) Solder resist is permitted in plated holes or vias in which no lead is to be soldered.
b.
For surface mount lands with no plated-through holes, the following shall apply:
(1) For lands with a pitch of .050 inch (1.27 mm) or greater, solder resist encroachment is on one side of
land only and does not exceed .002 inch (0.050 mm).
(2) For lands with a pitch less than .050 inch (1.27 mm), solder resist encroachment is on one side of land
only and does not exceed .001 inch (0.025 mm).
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