MIL-DTL-62739A(AT)
Department's System Command. Packaging data retrieval is available from the managing Military
Department's or Defense Agency's automated packaging files, CD-ROM products, or by
contacting the responsible packaging activity.
6. NOTES
(This section contains information of a general or explanatory nature which may be
helpful, but is not mandatory.)
6.1 Intended use. The PWA contains a 16-bit resetable real time clock with latch and
timing circuitry. High and low bytes of the latched clock data can be placed on BUS 0 - BUS 7
(board pins 21-28) independently. (Board pins will hereafter be referred to as P1-XX where
XX = the pin number.) The clock count is incremented at one fourth the frequency of the signal
at P1-45. The clock section also provides a Q pulse output (P1-42), a self-test output (P1-40),
and an EF4 output (P1-39). The Display Driver consists of four latches (U3, U4, U5, U6) which
can each latch 8 bits of data off BUS 0 - BUS 7. Each output of each latch drives the base input
of an open collector darlington transistor pair. When a logic level 1 is present at the base input,
the collector input of the darlington pair will sink current, lighting up a segment of an external
display which is pulled up to +5 Vdc. Connected to each of the collector inputs is a 510 ohm
resistor to ground which keeps the external display segment partially on when it is not being
driven by the darlington pair. The PWA also provides an output from U22, pin 11 to P1-41. The
PWA is military unique because it is designed specifically to be a component of the Simplified
Test Equipment/Internal Combustion Engine - Reprogrammable (STE/ICE-R) Vehicle Test Meter
(VTM), and to withstand environmental conditions which exceed commercial requirements.
6.2 Acquisition requirements. Acquisition documents must specify the following:
a. Title, number, and date of this specification.
b. PWA drawing number, revision letter, and date and PWA part number (see 3.2 and
3.5.2).
c. Issue of DoDISS to be cited in the solicitation, and if required, the specific issue of
individual documents referenced (see 2.2.1 and 2.3).
d. If first article inspection is required (see 3.1).
e. If CMOS logic levels should be other than as specified (see 3.3.2).
f. If marking is other than as specified (see 3.5.2).
g. If burn-in is not required (see 3.6.5).
h. If arrangements for first article inspection are other than as specified (see 4.1).
i. Whether ATE test is required (see table II footnote).
j. Packaging requirements (see 5.1).
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