MIL-DTL-62739A(AT)
4.2.3 Operating requirements verification.
4.2.3.1 Input power. To determine conformance to 3.3.1, the input current shall be
measured with an ammeter.
4.2.3.2 CMOS logic levels. To determine conformance to 3.3.2, the input and output
CMOS logic levels shall be observed and verified with an oscilloscope.
4.2.3.3 Input isolation.
4.2.3.3.1 Data bus isolation. To determine conformance to 3.3.3.1, the following
procedures shall be performed:
a. Connect a 10 ± 10% kilohm (kohm) resistor to each of the bus board pins (P1-21
thru P1-28). Terminate each of the 10 kohm resistors with a 20 ± 10% kohm
resistor to 5 V.
b. Apply 5 V to the connection between the 10 kohm and the 20 kohm resistors (the
test input) connected to P1-21. Apply 0.00 V to the other seven test inputs.
Verify that the voltage at P1-21 is not less than 4.5 V and the voltages at the other
seven bus board pins are not greater than 0.5 V.
c. Repeat part b for the seven remaining board pins P1-22 thru P1-28.
4.2.3.3.2 I/O, MRD/, and OEN-Q isolation. To determine conformance to 3.3.3.2, the
following procedures shall be performed:
a. Connect a 10 ± 10% kohm resistor to each of the board pins P1-29 thru P1-34,
P1-36, and P1-38.
b. Apply 5.00 V to the unterminated end (the test input) of the 10 kohm resistor
connected to P1-29. Apply 0.00 V to the other seven test inputs.
c. Verify that the voltage at P1-29 is not less than 4.5 V and the voltages at the other
seven test inputs are not greater than 0.5 V max.
d. Repeat parts b and c for P1-30 thru P1-34, P1-36 and P1-38.
4.2.3.4 Display driver outputs. To determine conformance to 3.3.4, the following
procedures shall be performed:
a. Connect a 270 ± 5% ohm resistor to each of the 32 display driver output board
pins, P1-49 thru P1-80. Connect the unterminated end of each 270 ohm resistor
to 5.00 V.
b. Write a hexadecimal bit pattern 00 to the bus (P1-21 thru P1-28) and apply the
waveforms in figure 2 to latch the test data into U3, U4, U5, and U6. Verify that
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