MIL-DTL-62739A(AT)
3.3.2 Complementary metal oxide semiconductor (CMOS) logic levels. Unless otherwise
specified (see 6.2), CMOS logic levels accepted by and output from the PWA shall be:
Input High (Logic Level 1) = 3.5 Vdc minimum (min)
Input Low (Logic Level 0) = 1.5 Vdc maximum (max)
Output High (Logic Level 1) = 4.5 Vdc min
Output Low (Logic Level 0) = 0.5 Vdc max
3.3.3 Input isolation. (NOTE: A "/" following a capitalized signal name denotes logic
negation.)
3.3.3.1 Data BUS isolation. Logic levels placed on a BUS input (P1-21 thru P1-28) shall
have no effect on nor be affected by logic levels present at any other BUS input.
3.3.3.2 I/O, MRD, and OEN-Q isolation. Logic levels present at any one of P1-29 thru
P1-34, P1-36, and P1-38 shall have no effect on nor be affected by logic levels present at any of
the other inputs specified in this paragraph.
3.3.4 Display driver outputs. Voltages appearing at a display output (P1-49 through
P1-80) shall have no influence on nor be influenced by voltages appearing at any other display
output. Display outputs, when pulled up to 5.0 V with a 270 ohm resistor, shall be capable of
sinking not less than 14.1 mA when active (logic level 1 at latch output) and not greater than
8.75 mA when inactive (logic level 0 at latch output).
3.3.5 Real time clock.
3.3.5.1 Clock clear. When a logic level 1 is applied to both P1-38 and P1-33, U22 pin 10
shall maintain a logic level 1 while U2 pins 3, 4, 5, 6, 11, 12, 13, 14 and U21 pins 3, 4, 5, 6, 11,
12, 13, and 14 shall maintain a logic level 0 regardless of any other inputs.
3.3.5.2 Q pulse. The Q pulse appearing at U16 pin 13 and P1-42 shall meet the timing
restrictions shown in figure 1.
3.3.5.3 Clock count and latch. The real time clock, when cleared and allowed to run for
Trun seconds at which time the data shall be latched into U1, U7, U20, and U15 by the Q pulse,
shall have the decimal equivalent of the 16-bit binary clock count of (Fin * Trun)/4; -0/+1 where:
Fin = the frequency of the clock signal applied to P1-45 and (16384/Fin) < Trun < (262140/Fin).
Trun shall be accurate and repeatable to five decimal places.
3.3.6 Automated testing equipment (ATE) test. The PWA shall pass TACOM approved
ATE test installed in TACOM approved ATE or equivalent.
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