MIL-DTL-62736A(AT)
4.2.3.5.2 CLEAR/. To determine conformance to 3.3.5.2, apply a logic level 0 to P1-62
and observe the logic level at P1-68.
4.2.3.5.3 States during power-up reset or CLEAR/. To determine conformance to
3.3.5.3, maintain a logic level 0 at P1-68 and observe the logic levels at the pins specified in
table II.
4.2.3.6 BUS transceiver.
4.2.3.6.1 Data in. To determine conformance to 3.3.6.1, verify that U4 pin 1 is at logic
level 0. Apply the logic levels in table III to P1-21 through P1-28 and observe the corresponding
logic levels in the table at U4 pins 2 through 9.
4.2.3.6.2 Extended I/O latch. To determine conformance to 3.3.6.2, verify that U4 pin 1
is at logic level 0. Apply the logic levels in table IV to P1-21 through P1-28 and latch them into
U9 by applying the waveforms in figure 2. Verify that the corresponding logic levels in the table
are present at U9 pins 2, 5, 7, 10, 12 and 15.
4.2.3.6.3 Extended I/O decoder. To determine conformance to 3.3.6.3, verify that U4
pin 1 is at logic level 0. Apply the logic levels in table V to P1-21 through P1-24 and latch them
into U9 by applying the waveforms in figure 2. Verify that the corresponding logic levels in the
table are present at U9 pins 10, 11, 12, 13, and 14.
4.2.3.6.4 BUS transceiver direction logic. To determine conformance to 3.3.6.4:
a. Apply a logic level 0 to P1-35 and a logic level 1 to P1-36. Verify that U4 pin 1 is
at logic level 0.
b. Apply a logic level 1 to P1-35 and a logic level 1 to P1-36. Verify that U4 pin 1 is
at logic level 0.
c. Apply logic level 0 to P1-35 and P1-36. Apply the first set of logic levels in
table XVIII to P1-21 through P1-28 and latch them into U9 by applying the
waveforms in figure 2. Apply a logic level 1 to P1-35 and P1-36. Verify that
U4 pin 1 is at logic level 1.
d. Repeat part c for the next byte in table XVIII.
TABLE XVIII. Extended I/O logic levels.
P1-
28
27
26
25
24
23
22
21
X
X
X
X
0
0
0
1
X
X
X
X
0
0
1
0
16
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