MIL-DTL-62736A(AT)
4.2.3.7 Multiply/divide unit (MDU).
4.2.3.7.1 MDU crystal oscillator. To determine conformance to 3.3.7.1, observe the
output of Y2 pin 8 with an oscilloscope.
4.2.3.7.2 MDU chip select logic. To determine conformance to 3.3.7.2:
a. Apply a logic level 0 to P1-35. Verify that U1 pin 23, U2 pin 11, and U3 pin 11
are at logic level 0.
b. Apply a logic level 1 to P1-35 and P1-57. Verify that U1 pin 23, U2 pin 11, and
U3 pin 11 are at logic level 0.
c. Apply a logic level 1 to P1-35. Apply logic level 0 to P1-36 and P1-57. Verify
that U1 pin 23, U2 pin 11, and U3 pin 11 are at logic level 1.
d. Apply a logic level 1 to P1-35 and P1-36. Apply a logic level 0 to P1-57. Verify
that U1 pin 23, U2 pin 11, and U3 pin 11 are at logic level 1.
4.2.3.7.3 MDU register selection. To determine conformance to 3.3.7.3, apply the logic
levels in table VIII at P1-21 through P1-26 and latch them into U9 by applying the waveforms in
figure 2.
4.2.3.7.4 MDU register load. To determine conformance to 3.3.7.4:
a. Select the MDU control register using the method of 4.2.3.7.3.
b. Apply the logic levels in table XIX at P1-21 through P1-28 and load them into the
MDU by applying the waveforms in figure 3.
c. Select the MDU X register using the method of 4.2.3.7.3 and repeat part b, once
for the high byte and once for the low byte.
d. Select the MDU Y register using the method of 4.2.3.7.3 and repeat part b, once
for the high byte and once for the low byte.
e. Select the MDU Z register using the method of 4.2.3.7.3 and repeat part b, once
for the high byte and once for the low byte.
TABLE XIX. MDU register load data.
MDU
High or
Data at P1-
Register
Low Byte
28
27
26
25
24
23
22
21
0
1
1
0
1
1
0
0
Control
High
1
0
1
0
1
0
1
0
X
High
0
1
0
1
0
1
0
1
Low
1
0
1
0
1
0
1
0
Y
High
Low
0
1
0
1
0
1
0
1
High
1
0
1
0
1
0
1
0
Z
Low
0
1
0
1
0
1
0
1
17
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