MIL-DTL-62737A(AT)
3.3.8.3 SRAM read. U8 pins 11 through 13, and 15 through 19 shall drive the data BUS
with logic levels defined by both the logic levels present at U8 pins 2 through 10, 21, 23 through
25, and data written by the requirement of paragraph 3.3.8.2, when the control signals
(MRD/ - U19-14 and RS/ -32-6) conform to the waveforms in figure 7.
3.3.8.4 EEPROM byte write. EPROM's, U2 through U7, shall be each capable of storing
the logic levels present at U1 pins 8 through 15 in a location defined by the logic levels present at
each EEPROM's address inputs (pins 2 through 10, 21, and 23 through 25) when
MWR/ (U20-17) and a chip select from table IX conform to the waveforms in figure 8.
TABLE IX. EEPROM chip select signals.
Signal
Chip select
Selected
name
line
device
CS1/
U26-15
U2
CS2/
U26-14
U3
CS3/
U26-12
U4
CS4/
U26-10
U5
CS5/
U26-9
U6
CS6/
U26-7
U7
3.3.8.5 EEPROM read. EEPROM's, U2 through U7, shall each be able to drive the data
BUS with logic levels defined by both the logic levels present at each EEPROM's address inputs
(pins 2 through 10, 21, and 23 through 25), and data written by the requirement of paragraph
3.3.8.4 when MRD/ (U19-14) and a chip select from table IX conform to the waveforms in
figure 9.
3.3.8.6 EEPROM page write. EEPROM's, U2 through U7, shall each be capable of
storing up to 16 bytes (the logic levels present at U1 pins 8 through 15) in locations defined by
the logic levels present at each EEPROM's address inputs (pins 2 through 10, 21, and 23 through
25; logic levels at pins 2 through 10, 21, and 23 through 25 must remain the same) when MWR/
(U20-17) and a chip select from table IX conform to the waveforms in figure 10.
3.3.9 ATE Test. The PWA shall pass TACOM approved ATE test installed in TACOM
approved ATE or equivalent.
3.3.10 Soldering. Soldering shall meet or exceed the requirements of
ANSI/IPC J-STD-001.
3.4 Interface requirements.
3.4.1 Overall envelope. Overall envelope of the PWA shall be in accordance with
drawing 12259256.
10
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