MIL-DTL-62737A(AT)
4.2.3.7.8 Extended I/O latches and decoder. To determine conformance to 3.3.7.8, a
logic analyzer shall be used to verify that logic levels present at U1 pins 15 through 11 appear at
U22 pins 2, 5, 7, 10, and 12 after the rising edge of OEN-Q (U28-12) when IOF/7 (U11-9) is at
logic level 1. The logic levels at U23, pins 15 through 13, shall be verified to conform to the
requirements of table IV.
4.2.3.7.9 Extended I/O data clocking. To determine conformance to 3.3.7.9, a logic
analyzer shall be used to verify that the rising edge of the signal at the active port clock, as
specified by table V, occurs after the rising edge of OEN-Q/ when IOF/7 is at logic level 1.
4.2.3.7.10 Microprocessor clock frequency select. To determine conformance to
3.3.7.10, a logic analyzer shall be used to verify that the signals at U13 pins 1, 3, 5, 6, 9, 11,
and 12 conform to the waveforms of figure 4 when selected by the requirements of 3.3.7.8 and
clocked by the requirements of 3.3.7.9.
4.2.3.7.11 Memory bank select. To determine conformance to 3.3.7.11, a logic analyzer
shall be used to verify that the level at U25-5 is equivalent to the logic level at U1-15 when
selected by the requirements of paragraph 3.3.7.8 and clocked by the requirements of paragraph
3.3.7.9.
4.2.3.7.12 Bootstrap EPROM page select. To determine conformance to 3.3.7.12, a
logic analyzer shall be used to verify that the logic levels at U24-5 and U24-9 are equivalent to the
logic levels at U1-15 and U1-14 when selected by the requirements of 3.3.7.8 and clocked by the
requirements of 3.3.7.9.
4.2.3.7.13 Memory chip select. To determine conformance to 3.3.7.13, a logic analyzer
shall be used to verify that the memory chip select outputs conform to the requirements of
tables VI and VII.
4.2.3.8 Memory.
4.2.3.8.1 Bootstrap EPROM read. To determine conformance to 3.3.8.1, a logic
analyzer shall be used to verify the logic levels on the data BUS (see 6.3) when valid address and
control signals are supplied to U9 as shown in the waveforms of figure 5.
4.2.3.8.2 SRAM write. To determine conformance to 3.3.8.2, U8 shall be written to by
supplying the control signals and valid data as shown in the waveforms of figure 6. The method
of 4.2.3.8.3 shall be used for verification.
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