MIL-DTL-62737A(AT)
TABLE IV. Extended I/O decoder outputs.
U22 Pin
U23 Pin
Port
12
10
7
5
2
13
14
15
address
Function
X
0
X
X
X
0
0
0
---
---
0
1
0
0
0
0
0
1
08 Hex
2 MHz CPU
1
1
0
0
0
0
0
1
18 Hex
4 MHz CPU
X
1
0
0
1
0
1
0
09 Hex
CNTR
X
1
0
1
0
1
0
0
0A Hex
MSEL
X
1
X
1
1
0
0
0
---
---
X
1
1
X
X
0
0
0
---
---
(X denotes a don't care condition)
3.3.7.9 Extended I/O data clocking. Logic levels present at U1 pins 8 through 15 shall be
clocked into a previously selected extended I/O port (certain data BUS bits may not be
connected) at the rising edge of OEN-Q/ U28-6) when IOF/7 (U11/9) is at logic level 1. Table V
shows the active port clock as a function of the selected extended I/O port.
TABLE V. Extended I/O port clocks.
Selected
Port
port address
Function
clock
08 Hex
2 MHz CPU
U28-8
18 Hex
4 MHz CPU
U28-8
09 Hex
CNTR
U29-12
0A Hex
MSEL
U29-6
3.3.7.10 Microprocessor clock frequency select. The clock input to the microprocessor
shall be able to change between 2 MHz and 4 MHz frequencies according to the waveforms in
figure 4 when selected by the requirement of paragraph 3.3.7.8. Paragraph 3.3.7.9 shall be used
to clock the frequency selection of paragraph 3.3.7.8 using "don't care" conditions for data.
3.3.7.11 Memory bank select. The memory bank select line, MSEL (U25-5), when
selected by the requirement of paragraph 3.3.7.8, shall have a logic level equivalent to the logic
level at U1-15 when clocked by the requirement of paragraph 3.3.7.9.
3.3.7.12 Bootstrap EPROM page select. The control lines, CNTR1 (U24-5) and CNTR2
(U24-9), when selected by the requirement of paragraph 3.3.7.8, shall have logic levels equivalent
to the logic levels at U1 pins 15 and 14, respectively, when clocked by the requirement of
paragraph 3.3.7.9.
3.3.7.13 Memory chip select. The memory chip select line U26 pins 13, 7, 9, 10, 12, 14,
and 15 and U27 pins 13 and 15 shall have the logic levels shown in tables VI and VII for the
output from U10 pins 15, 16, and 19, U33-5, and U25-5.
8
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