MIL-DTL-62737A(AT)
3.3.4.4 Power-up/down memory protection. Whenever the voltage at P1 pins 5 and 6
goes below 4.5 V, U33-5 shall maintain a voltage of no more than 0.4 V until the voltage at P1
pins 5 and 6 is less than 3.0 V. The voltage at U33-5 shall track the voltage at P1 pins 5 and 6.
If the voltage at P1 pins 5 and 6 increases to a voltage greater than 4.6 V from a voltage less than
4.5 V, U33-5 shall maintain an output voltage of not greater than 0.4 V for a period of not less
than 208 milliseconds (ms) and return to the voltage present at P1 pins 5 and 6 within 312 ms.
3.3.5 Clock frequencies.
3.3.5.1 Clock oscillator. The frequency of the signal at Y1-8, U12-3, and U15-1 shall be
4.000 megahertz (MHz) + 4.00 kilohertz (kHz).
3.3.5.2 2 MHz clock. The frequency of the signal at P1-83 and U12-2 shall be
2.000 MHz + 400 Hz.
3.3.5.3 400 kHz clock. The frequency of the signal at P1-67 and U14-2 shall be
400.0 kHz + 400 Hz.
3.3.5.4 200 kHz clock. The frequency of the signal at P1-70 shall be 200.0 kHz
+ 200 Hz.
3.3.6 Microprocessor outputs and inputs.
3.3.6.1 High order byte address latch. When TPA (U1-34) goes from logic level 1 to
logic level 0, the logic levels present at U1-25 through U1-32 shall be latched into U10 and shall
be present at pins, 2, 5, 6, 9, 12, 15, 16 and 19, respectively, after the falling edge of TPA.
3.3.6.2 Microprocessor inputs. A logic level 0 applied at any microprocessor input
(P1-49 through P1-54 and P1-56) shall cause the corresponding pins of U1 (38, 36, 37, 24, 21,
23, and 22, respectively) to be at logic level 0. The applied logic level shall be capable of sinking
not less than 175 microamperes (µA).
3.3.7 Board logic and functions.
3.3.7.1 I/O port decoder. U11 shall have outputs shown in table III at P1-29 through
P1-35 for the corresponding inputs at U11 pins 2, 3, and 14 between the time that TPA (U1-34)
goes from logic level 1 to logic level 0 and the time that TPB (U1-33) goes from logic level 0 to
logic level 1.
3.3.7.2 OEN-Q. The OEN-Q signal shall conform to the waveform in figure 2 when the
Q output (U1-4) is at logic level 1.
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