MIL-DTL-62737A(AT)
4.2.3.6 Microprocessor outputs and inputs.
4.2.3.6.1 High order byte address latch. To determine conformance to 3.3.6.1, a logic
analyzer shall be used to verify that the logic levels present at U1-25 through U1-32 are present at
U10 pins 2, 5, 6, 9, 12, 15, 16, and 19 after the falling edge of TPA (U1-34).
4.2.3.6.2 Microprocessor inputs. To determine conformance to 3.3.6.2, a logic level 0
shall be applied at P1-49 through P1-54 and P1-56. A logic level 0 shall be verified to be present
at U1 pins 38, 36, 37, 24, 21, 23, and 22, respectively. An ammeter shall be used to verify that
the current at P1-49 through P1-54 and P1-56 is not greater than 175 microamperes.
4.2.3.7 Board logic and functions.
4.2.3.7.1 I/O port decoder. To determine conformance to 3.3.7.1, the logic levels at U11
pins 5 through 7 and 9 through 12 shall be verified to correspond to the logic levels present at
U1-19, U-18, and U1-17 given in table V between the falling edge of TPA (U1-34) and the rising
edge of TPB (U1-33).
4.2.3.7.2 OEN-Q. To determine conformance to 3.3.7.2, a logic analyzer shall be used to
verify that the signal at U28-12 conforms to the waveforms of figure 2 when the Q output (U1-4)
is set to a logic level 1.
4.2.3.7.3 OEN-Q/. To determine conformance to 3.3.7.3, a logic analyzer shall be used
to verify that the signal at U26-6 conforms to the waveforms of figure 3 when the Q output
(U1-4) is set to a logic level 0.
4.2.3.7.4 Data BUS transceiver logic. To determine conformance to 3.3.7.4, a logic
analyzer shall be used to verify that a logic level 0 is present at U30-8 when U19-14 and either
U1-19, U1-16, or U1-17 are at logic level 1.
4.2.3.7.5 Data BUS inputs. To determine conformance to 3.3.7.5, a logic analyzer shall
be used to verify that the logic levels applied at P1-21 through P1-28 are present at U21 pins 9, 8,
7, 6, 5, 4, 3, and 2 only when U30-8 is at logic level 0.
4.2.3.7.6 External input logic. To determine conformance to 3.3.7.6, a logic analyzer
shall be used to verify that a logic level 0 is present at U30-11 when U11-7 and U19-14 are at
logic level 1.
4.2.3.7.7 External inputs. To determine conformance to 3.3.7.7, a logic analyzer shall be
used to verify that the logic levels present at P1-76, P1-77, P1-79, P1-81, P1-69, P1-71, P1-73,
and P1-75 are present at U17 pins 12, 9, 5, 6, 16, 15, 19, and 2 only when U30-11 is at logic
level 0.
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