MIL-DTL-62737A(AT)
(Application for copies should be addressed to the American National Standard Institute,
11 West 42nd Street, New York, NY 10036.)
2.4 Order of precedence. In the event of a conflict between the text of this document and
the references cited herein, the text of this document takes precedence. Nothing in this document,
however, supersedes applicable laws and regulations unless a specific exemption has been
obtained.
3. REQUIREMENTS
3.1 First article. When specified (see 6.2), a sample shall be subjected to first article
inspection in accordance with 4.1.1.
3.2 Design, materials, and manufacturing processes. Design, materials, and
manufacturing process selection shall be as specified herein and in applicable referenced
specifications, standards, and drawings. Materials shall be uniform and free from imperfections or
defects which affect their performance and serviceability. All metallic parts shall be made from
corrosion resistant metals or treated with corrosion-resistant materials. Asbestos and Cadmium
materials shall not be used in any form in any part of the PWA. No item, part or assembly shall
contain radioactive materials in which the specific activity is greater than 0.002 microcuries per
gram or activity per item equals or exceeds 0.01 microcuries.
3.2.1 Recycled, recovered, or environmentally preferable materials. Recycled, recovered,
or environmentally preferable materials should be used to the maximum extent possible provided
that the material meets or exceeds the operational and maintenance requirements, and promotes
economically advantageous life cycle costs.
3.3 Operating requirements. Each PWA shall provide the following functional,
operational, and performance capabilities.
3.3.1 Input power. The PWA shall not require more than the current specified in table I.
TABLE I. Input power.
Source
Voltage
Current
P1-5, 6
+5 Vdc 1/
285 mA 2/
1/ Vdc = Volts direct current
2/ mA = milliampere
3.3.2 Complimentary metal oxide semiconductor (CMOS) logic levels. Unless otherwise
specified (see 6.2), CMOS logic levels accepted by and output from the PWA shall be as follows:
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