MIL-DTL-62737A(AT)
a. Connect a 10k (where k = 1000) + 10% ohm resistor to each of the board pins
P1-50, P1-52, P1-53, P1-54, P1-56, and P1-62.
b. Apply 5.00 V to the unterminated end (the test input) of the 10 kilohms (kohm)
resistor connected to P1-50. Apply 0.00 V to the other seven test inputs.
c. Verify that the voltage at P1-50 is not less than 4.5 V and the voltages at the other
seven test inputs are not greater and 0.5 V.
d. Repeat parts (b) and (c) for P1-52, P1-53, P1-54, P1-56, and P1-62.
4.2.3.3.2 External input isolation. To determine conformance to 3.3.3.2, the following
procedures shall be performed:
a. Connect a 10k + 10% ohm resistor to each of the board pins P1-76, P1-77, P1-79,
P1-81, P1-69, P1-71, P1-73, and P1-75.
b. Apply 5.00 V to the unterminated end (the test input) of the 10 kohm resistor
connected to P1-76. Apply 0.00 V to the other seven test inputs.
c. Verify that the voltage at P1-76 is not less than 4.5 V and the voltages at the other
seven test inputs are not greater than 0.5 V.
d. Repeat parts (b) and (c) for P1-77, P1-79, P1-81, P1-69, P1-71, P1-73, and
P1-75.
4.2.3.4 Reset.
4.2.3.4.1 Power-up reset. To determine conformance to 3.3.4.1, +5.00 Vdc shall be
applied to P1-5 and P1-6 and the voltage shall be observed at P1-68, U30-6, U1-3, U13 pins 1,
13, U22-1, U24 pins 4, 10, and U25-4 for compliance with figure 1.
4.2.3.4.2 CLEAR/. To determine conformance to 3.3.4.2, a logic level 0 shall be applied
to P1-62 and the logic level shall be observed at P1-68.
4.2.3.4.3 States during power-up reset or CLEAR/. To determine conformance to
3.3.4.3, a logic level 0 shall be maintained at P1-68 and the logic levels shall be observed at the
pins specified in table II.
4.2.3.4.4 Power-up/down memory protection. To determine conformance to 3.3.4.4,
5.0 Vdc shall be applied to P1 pins 5 and 6 for at least 1 second and the voltage at U33-5 shall be
verified to be 5 Vdc. The voltage at P1 pins 5 and 6 shall be reduced to a voltage less than
4.5 Vdc. The voltage applied to P1 pins 5 and 6 shall be increased to a voltage between 4.6 Vdc
and 5.0 Vdc. The voltage at U33-5 shall be verified to maintain a voltage not greater than
0.4 Vdc for at least 208 ms and return to the voltage applied to P1 pins 5 and 6 within 312 ms.
4.2.3.5 Clock frequencies. To determine conformance to 3.3.5.1 through 3.3.5.4, the
frequency of the signal as required shall be observed with an oscilloscope.
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